In multi-signal data transfer, for example, multi-wire differential signaling such as 3-phase or N-factorial low-voltage differential signaling (LVDS), transcoding (e.g., the digital-to-digital data conversion of one encoding type to another) may be done to embed symbol clock information by causing symbol transition at every symbol cycle, instead of sending clock information in separate data lanes (differential transmission paths). Embedding clock information by such transcoding is an effective way to minimize skew between clock and data signals, as well as to eliminate the necessity of a phase-locked loop (PLL) to recover the clock information from the data signals.
Clock and data recovery (CDR) circuits are decoder circuits that extract data signals as well as a clock signals from multiple data signals. However, clock recovery from multiple data signals whose state transitions represent clock events often suffers unintended spike pulses on its recovered clock signal due to inter-lane skew of the data signals or glitch signals by intermediate or undeterminable data signal states at data transition times.
Therefore, an efficient glitch removal circuit is needed that minimizes analog delays and is scalable in multi-signal systems having different numbers of conductors.